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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADV7123 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 cmos, 240 mhz triple 10-bit high speed video dac functional block diagram r9Cr0 gnd r set ior ior comp ADV7123 v ref voltage reference circuit g9Cg0 b9Cb0 iog iog iob iob psave power-down mode blank sync clock v aa dac 10 data register 10 dac 10 data register 10 dac 10 data register 10 blank and sync logic features 240 msps throughput rate triple 10-bit d/a converters sfdr C70 db at f clk = 50 mhz; f out = 1 mhz C53 db at f clk = 140 mhz; f out = 40 mhz rs-343a/rs-170 compatible output complementary outputs dac output current range 2 ma to 26 ma ttl-compatible inputs internal reference (1.23 v) single supply +5 v/+3.3 v operation 48-lead lqfp package low power dissipation (30 mw min @ 3 v) low power standby mode (6 mw typ @ 3 v) industrial temperature range (C40 8 c to +85 8 c) applications digital video systems (1600 3 1200 @ 100 hz) high resolution color graphics digital radio modulation image processing instrumentation video signal reconstruction general description the ADV7123 (adv ? ) is a triple high speed, digital-to-analog conver ter on a single monolithic chip. it consists of three high speed, 10-bit, video d/a converters with complementary outputs, a standard ttl input interface and a high impedance, analog output current source. the ADV7123 has three separate 10-bit-wide input ports. a single +5 v/+3.3 v power supply and clock are all that are required to make the part functional. the ADV7123 has addi- tional video control signals, composite sync and blank . the ADV7123 also has a power-save mode. the ADV7123 is fabricated in a +5 v cmos process. its monolithic cmos construction ensures greater functionality with lower power dissipation. the ADV7123 is available in a 48-lead lqfp package. product highlights 1. 240 msps throughput. 2. guaranteed monotonic to 10 bits. 3. compatible with a wide variety of high resolution color graphics systems including rs-343a and rs-170a. adv is a registered trademark of analog devices, inc.
C2C rev. a ADV7123Cspecifications 5 v specifications parameter min typ max units test conditions 1 static performance resolution (each dac) 10 bits integral nonlinearity (bsl) C1 0.4 +1 lsb differential nonlinearity C1 0.25 +1 lsb guaranteed monotonic digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 v input current, i in C1 +1 m av in = 0.0 v or v dd psave pull-up current 20 m a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high output current 2.0 18.5 ma r/g/b dac, sync = low dac to dac matching 1.0 5 % output compliance range, v oc 0 +1.4 v output impedance, r out 100 k w output capacitance, c out 10 pf i out = 0 ma offset error C0.025 +0.025 % fsr tested with dac output = 0 v gain error 2 C5.0 +5.0 % fsr fsr = 17.62 ma voltage reference (ext. and int.) reference range, v ref 1.12 1.235 1.35 v power dissipation digital supply current 3 3.4 9 ma f clk = 50 mhz digital supply current 3 10.5 15 ma f clk = 140 mhz digital supply current 3 18 25 ma f clk = 240 mhz analog supply current 67 72 ma r set = 560 w analog supply current 8 ma r set = 4933 w standby supply current 4 2.1 5.0 ma psave = low, digital and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% notes 1 temperature range t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to 70 c at 240 mhz. 2 gain error = (measured (fsc)/ideal (fsc) C1) 100), where ideal = v ref /r set k (3ffh) and k = 7.9896. 3 digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 v and v dd . 4 these max/min specifications are guaranteed by characterization to be over 4.75 v to 5.25 v range. specifications subject to change without notice. (v aa = +5 v 6 5%, v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 1 unless otherwise noted, t j max = 110 8 c)
C3C rev. a ADV7123 3.3 v specifications 1 parameter min typ max units test conditions 2 static performance resolution (each dac) 10 bits r set = 680 w integral nonlinearity (bsl) C1 0.5 +1 lsb r set = 680 w differential nonlinearity C1 0.25 +1 lsb r set = 680 w digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input current, i in C1 +1 m av in = 0.0 v or v dd psave pull-up current 20 m a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high output current 2.0 18.5 ma r/g/b dac, sync = low dac to dac matching 1.0 % output compliance range, v oc 0 +1.4 v output impedance, r out 70 k w output capacitance, c out 10 pf offset error 0 0 % fsr tested with dac output = 0 v gain error 3 0 % fsr fsr = 17.62 ma voltage reference (ext.) reference range, v ref 1.12 1.235 1.35 v voltage reference (int.) reference range, v ref 1.235 v power dissipation digital supply current 4 2.2 5.0 ma f clk = 50 mhz digital supply current 4 6.5 12.0 ma f clk = 140 mhz digital supply current 4 11 15 ma f clk = 240 mhz analog supply current 67 72 ma r set = 560 w analog supply current 8 ma r set = 4933 w standby supply current 2.1 5.0 ma psave = low, digital and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% notes 1 these max/min specifications are guaranteed by characterization to be over 3.0 v to 3.6 v range. 2 temperature range t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to 70 c at 240 mhz. 3 gain error = (measured (fsc)/ideal (fsc) C1) 100), where ideal = v ref /r set k (3ffh) and k = 7.9896. 4 digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 v and v dd . specifications subject to change without notice. (v aa = +3.0 v C3.6 v, v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 2 unless otherwise noted, t j max = 110 8 c)
C4C rev. a ADV7123Cspecifications 5 v dynamic specifications 1 parameter min typ max units ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = +25 c 66 dbc t min to t max 65 dbc f clk = 50 mhz; f out = 2.00 mhz 64 dbc f clk = 100 mhz; f out = 2.00 mhz 63 dbc f clk = 140 mhz; f out = 2.00 mhz 55 dbc dac performance glitch impulse 10 pvs dac crosstalk 3 23 db data feedthrough 4, 5 22 db clock feedthrough 4, 5 33 db notes 1 these max/min specifications are guaranteed by characterization over 4.75 v to 5.25 v range. 2 note that the ADV7123 exhibits high performance when operating with an internal voltage reference, v ref . 3 dac to dac crosstalk is measured by holding one dac high while the other two are making low to high and high to low transitions . 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse includ es clock and data feedthrough. 5 ttl input values are 0 v to 3 v, with input rise/fall times 3 ns, measured the 10% and 90% points. timing reference points is 50% for inputs and outputs. specifications subject to change without notice. (v aa = +5 v 6 5% 1 , v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications are for t a = +25 8 c unless otherwise noted, t j max = 110 8 c)
C5C rev. a ADV7123 3.3 v dynamic specifications parameter min typ max units ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = +25 c 66 dbc t min to t max 65 dbc f clk = 50 mhz; f out = 2.00 mhz 64 dbc f clk = 100 mhz; f out = 2.00 mhz 64 dbc f clk = 140 mhz; f out = 2.00 mhz 55 dbc dac performance glitch impulse 10 pvs dac crosstalk 3 23 db data feedthrough 4, 5 22 db clock feedthrough 4, 5 33 db notes 1 these max/min specifications are guaranteed by characterization over 3.0 v to 3.6 v range. 2 note that the ADV7123 exhibits high performance when operating with an internal voltage reference, v ref . 3 dac to dac crosstalk is measured by holding one dac high while the other two are making low to high and high to low transitions . 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse includ es clock and data feedthrough. 5 ttl input values are 0 v to 3 v, with input rise/fall times 3 ns, measured the 10% and 90% points. timing reference points is 50% for inputs and outputs. specifications subject to change without notice. (v aa = +3.0 vC3.6 v 1 , v ref = 1.235 v, r set = 680 v , c l = 10 pf. all specifications are t a = +25 8 c unless otherwise noted, t j max = 110 8 c)
ADV7123 C6C rev. a 5 v timingCspecifications 1 parameter min typ max units condition analog outputs analog output delay, t 6 5.5 ns analog output rise/fall time, t 7 4 1.0 ns analog output transition time, t 8 5 15 ns analog output skew, t 9 6 12 ns clock control f clk 7 0.5 50 mhz 50 mhz grade f clk 7 0.5 140 mhz 140 mhz grade f clk 7 0.5 240 mhz 240 mhz grade data and control setup, t 1 1.5 ns data and control hold, t 2 2.5 ns clock pulsewidth high, t 4 1.875 1.1 ns f max = 240 mhz clock pulsewidth low t 5 1.875 1.25 ns f max = 240 mhz clock pulsewidth high t 4 2.85 ns f max = 140 mhz clock pulsewidth low t 5 2.85 ns f max = 140 mhz clock pulsewidth high t 4 8.0 ns f max = 50 mhz clock pulsewidth low t 5 8.0 ns f max = 50 mhz pipeline delay, t pd 6 1.0 1.0 1.0 clock cycles psave up time, t 10 6 210 ns notes 1 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 2 these maximum and minimum specifications are guaranteed over this range. 3 temperature range: t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a ful l-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk max specification production tested at 125 mhz and 5 v limits specified here are guaranteed by characterization. specifications subject to change without notice. (v aa = +5 v 6 5% 2 , v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 3 unless otherwise noted, t j max = 110 8 c)
ADV7123 C7C rev. a 3.3 v timingCspecifications 1 parameter min typ max units condition analog outputs analog output delay, t 6 7.5 ns analog output rise/fall time, t 7 4 1.0 ns analog output transition time, t 8 5 15 ns analog output skew, t 9 6 12 ns clock control f clk 7 50 mhz 50 mhz grade f clk 7 140 mhz 140 mhz grade f clk 7 240 mhz 240 mhz grade data and control setup, t 1 1.5 ns data and control hold, t 2 2.5 ns clock pulsewidth high, t 4 1.1 ns f max = 240 mhz clock pulsewidth low t 5 1.4 ns f max = 240 mhz clock pulsewidth high t 4 2.85 ns f max = 140 mhz clock pulsewidth low t 5 2.85 ns f max = 140 mhz clock pulsewidth high t 4 8.0 ns f max = 50 mhz clock pulsewidth low t 5 8.0 ns f max = 50 mhz pipeline delay, t pd 6 1.0 1.0 1.0 clock cycles psave up time, t 10 6 410 ns notes 1 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 2 these maximum and minimum specifications are guaranteed over this range. 3 temperature range: t min to t max : C40 c to +85 c at 50 mhz and 140 mhz, 0 c to +70 c at 240 mhz. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a ful l-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk max specification production tested at 125 mhz and 5 v limits specified here are guaranteed by characterization. specifications subject to change without notice. t 2 clock data notes: 1. output delay ( t 6 ) measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 2. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full-scale transition. 3. transition time ( t 8 ) measured from the 50% point of full-scale transition to within 2% of the final output value. analog outputs (ior, ior , iog, iog , iob, iob ) digital inputs (r9Cr0, g9Cg0, b9Cb0, sync , blank ) t 3 t 4 t 5 t 1 t 8 t 6 t 7 figure 1. timing diagram (v aa = +3.0 vC3.6 v 2 , v ref = 1.235 v, r set = 560 v , c l = 10 pf. all specifications t min to t max 3 unless otherwise noted, t j max = 110 8 c)
ADV7123 C8C rev. a ordering information speed options package 50 mhz 1 140 mhz 1 240 mhz 2 plastic lqfp (st-48) ADV7123kst50 ADV7123kst140 ADV7123jst240 notes 1 specified for C40 c to +85 c operation. 2 specified for 0 c to +70 c operation. absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v voltage on any digital pin . . . . . gnd C 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . C40 c to +85 c storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . 220 c i out to gnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 r3 psave r8 r2 r6 r5 r7 r0 r1 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) v ref comp ior ior iog iog v aa b4 v aa b0 b1 b2 b3 b5 g0 g1 g2 g3 g4 g5 g6 g7 g8 g9 sync v aa iob iob gnd b6 b7 b8 b9 r set ADV7123 clock blank gnd r9 r4 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7123 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ADV7123 C9C rev. a pin function descriptions pin mnemonic function blank composite blank control input (ttl compatible). a logic zero on this control input drives the analog outputs, ior, iob and iog, to the blanking level. the blank signal is latched on the rising edge of clock. while blank is a logical zero, the r0Cr9, g0Cg9 and r0Cr9 pixel inputs are ignored. sync composite sync control input (ttl compatible). a logical zero on the sync input switches off a 40 ire current source. this is internally connected to the iog analog output. sync does not override any other control or data input, therefore, it should only be asserted during the blanking interval. sync is latched on the rising edge of clock. if sync information is not required on the green channel, the sync input should be tied to logical zero. clock clock input (ttl compatible). the rising edge of clock latches the r0Cr9, g0Cg9, b0Cb9, sync and blank pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. r0Cr9, red, green and blue pixel data inputs (ttl compatible). pixel data is latched on the rising edge of clock. g0Cg9, r0, g0 and b0 are the least significant data bits. unused pixel data inputs should be connected to either the b0Cb9 regular pcb power or ground plane. ior, iog, iob red, green, and blue current outputs. these high impedance current sources are capable of directly driving a doubly terminated 75 w coaxial cable. all three current outputs should have similar output loads whether or not they are all being used. ior , iog , iob differential red, green and blue current outputs (high impedance current sources). these rgb video outputs are specified to directly drive rs-343a and rs-170 video levels into a doubly terminated 75 w load. if the complementary outputs are not required, these outputs should be tied to ground. psave power save control pin. reduced power consumption is available on the ADV7123 when this pin is active. r set a resistor (r set ) connected between this pin and gnd, controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-scale output current. the relationship between r set and the full-scale output current on iog (assuming i sync is connected to iog) is given by: r set ( w ) = 12,081 v ref (v)/iog (ma) the relationship between r set and the full-scale output current on ior, iog and iob is given by: iog (ma) = 12,081 v ref (v)/r set ( w ) ( sync being asserted) ior, iob (ma) = 8,627 v ref (v)/r set ( w ) the equation for iog will be the same as that for ior and iob when sync is not being used, i.e., sync tied permanently low. comp compensation pin. this is a compensation pin for the internal reference amplifier. a 0.1 m f ceramic capacitor must be connected between comp and v aa . v ref voltage reference input for dacs or voltage reference output (1.235 v) v aa analog power supply (5 v 5%). all v aa pins on the ADV7123 must be connected. gnd ground. all gnd pins must be connected.
ADV7123 C10C rev. a terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level that will shut off the picture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three pri- mary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. sync signal ( sync ) the position of the composite video signal that synchronizes the scanning process. gray scale the discrete levels of video signal between reference black and reference white levels. a 10-bit dac contains 1024 different levels, while an 8-bit dac contains 256. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. sync level the peak level of the sync signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion that may be visually observed.
ADV7123 C11C rev. a 5 vCtypical performance characteristics (v aa = +5 v, v ref = 1.235 v, i out = 17.62 ma, 50 v doubly terminated load, differential output loading, t a = +25 8 c) f out C mhz 70 0 0.1 100 1 sfdr C dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 sfdr (de) sfdr (se) figure 2. sfdr vs. f out @ f clock = 140 mhz (single ended and differential) f clock C mhz 74 58 thd C dbc 50 100 140 72 70 68 64 60 66 76 62 0 160 4th harmonic 3rd harmonic 2nd harmonic figure 5. thd vs. f clock @ f out = 2 mhz (2nd, 3rd and 4th harmonics) 0khz start C85.0 sfdr C dbm C45.0 C5.0 35.0mhz 70.0mhz stop figure 8. single-tone sfdr @ f clock = 140 mhz (f out1 = 2 mhz) f out C mhz 70 0 0.1 100 1 sfdr C dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 80 sfdr (se) sfdr (de) figure 3. sfdr vs. f out @ f clock = 50 mhz (single ended and differential) i out C ma 0.9 0 linearity C lsbs 2 17.62 0.8 0.7 0.6 0.4 0.2 0.5 1 0.3 020 0.1 figure 6. linearity vs. i out 0khz start C85.0 sfdr C dbm C45.0 C5.0 35.0mhz 70.0mhz stop figure 9. single-tone sfdr @ f clock = 140 mhz (f out1 = 20 mhz) temperature C 8 c 71.8 70.4 sfdr C dbc +25 +85 71.6 71.4 71.2 70.8 70.6 71 72 C10 figure 4. sfdr vs. temperature @ f clock = 50 mhz (f out = 1 mhz) code C inl C1.00 error C lsb 0.50 C0.50 0.00 1.00 0.75 1023 C0.16 figure 7. typical linearity (inl) 0khz start C85.0 sfdr C dbm C45.0 C5.0 35.0mhz 70.0mhz stop figure 10. dual-tone sfdr @ f clock = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
ADV7123 C12C rev. a 3 vCtypical performance characteristics (v aa = +3 v, v ref = 1.235 v, i out = 17.62 ma, 50 v doubly terminated load, differential output loading, t a = +25 8 c) f out C mhz 70 0 0.1 100 sfdr C dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 sfdr (se) sfdr (de) figure 11. sfdr vs. f out @ f clock = 140 mhz (single ended and differential) frequency C mhz 74 58 thd C dbc 50 100 140 72 70 68 64 60 66 76 62 0 160 2nd harmonic 3rd harmonic 4th harmonic figure 14. thd vs. f clock @ f out = 2 mhz (2nd, 3rd and 4th harmonics) 0khz start C85.0 sfdr C dbm C45.0 C5.0 35.0mhz 70.0mhz stop figure 17. single-tone sfdr @ f clock = 140 mhz (f out1 = 2 mhz) f out C mhz 70 0 0.1 100 1 sfdr C dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 80 sfdr (se) sfdr (de) figure 12. sfdr vs. f out @ f clock = 140 mhz (single ended and differential) i out C ma 0.9 0 linearity C lsbs 2 17.62 0.8 0.7 0.6 0.4 0.2 0.5 1 0.3 020 0.1 figure 15. linearity vs. i out 0khz start C85.0 sfdr C dbm C45.0 C5.0 35.0mhz 70.0mhz stop figure 18. single-tone sfdr @ f clock = 140 mhz (f out1 = 20 mhz) temperature C 8 c 71.8 70.4 sfdr C dbc 20 85 145 71.6 71.4 71.2 70.8 70.6 71 72 165 0 figure 13. sfdr vs. temperature @ f clock = 50 mhz, (f out = 1 mhz) code C inl C1.00 linearity C lsb 0.50 C0.50 0.00 1.00 0.75 1023 C0.42 figure 16. typical linearity 0khz start C85.0 sfdr C dbm C45.0 C5.0 35.0mhz 70.0mhz stop figure 19. dual-tone sfdr @ f clock = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
ADV7123 C13C rev. a circuit description and operation the ADV7123 contains three 10-bit d/a converters, with three input channels, each containing a 10-bit register. also integrated on board the part is a reference amplifier. crt con trol func tions blank and sync are integrated on board the ADV7123. digital inputs thirty bits of pixel data (color information) r0Cr9, g0Cg9 and b0Cb9 are latched into the device on the rising edge of each clock cycle. this data is presented to the three 10-bit dacs and then converted to three analog (rgb) output waveforms. see figure 20. clock data analog outputs (ior, ior, iob ior , iog , iob ) digital inputs (r9-r0, g9-g0, b9-b0, sync , blank ) figure 20. video data input/output the ADV7123 has two additional control signals that are latched to the analog video outputs in a similar fashion. blank and sync are each latched on the rising edge of clock to maintain synchronization with the pixel data stream. the blank and sync functions allow for the encoding of these video synchronization signals onto the rgb video output. this is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the blank and sync digital inputs. figure 21 shows the analog output, rgb video waveform of the ADV7123. the influence of sync and blank on the analog video waveform is illustrated. table i details the resultant effect on the analog outputs of blank and sync . all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the ADV7123 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and hence the required clock frequency, will be determined by the on-screen resolution, according to the following equation: dot rate = ( horiz res ) ( vert res ) ( refresh rate )/ ( retrace factor ) horiz res = number of pixels/line. vert res = number of lines/frame. refresh rate = horizontal scan rate. this is the rate at which the screen must be refreshed, typically 60 hz for a noninterlaced sys- tem or 30 hz for an interlaced system. retrace factor = total blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). table i. video output truth table (r set = 530 v , r load = 37.5 v ) dac description iog (ma) iog (ma) ior/iob ior/iob sync blank input data white level 26.67 0 18.62 0 1 1 3ffh video video + 8.05 18.62 C video video 18.62 C video 1 1 data video to blank video 18.62 C video video 18.62 C video 0 1 data black level 8.05 18.62 0 18.62 1 1 000h black to blank 0 18.62 0 18.62 0 1 000h blank level 8.05 18.62 0 18.62 1 0 xxxh sync level 0 18.62 0 18.62 0 0 xxxh red, blue green ma v ma v 18.62 0.7 26.67 1.000 0 0 8.05 0.3 00 white level blank level sync level 100 ire 43 ire notes: 1. outputs connected to a doubly terminated 75 v load. 2. v ref = 1.235v, r set = 530 v . 3. rs-343a levels and tolerances assumed on all levels. figure 21. rgb video output waveform
ADV7123 C14C rev. a therefore, if we have a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate and a retrace factor of 0.8, then: dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the ADV7123 on the rising edge of clock, as previously described in the digital inputs section. it is recommended that the clock input to the ADV7123 be driven by a ttl buffer (e.g., 74f244). video synchronization and control the ADV7123 has a single composite sync ( sync ) input con- trol. many graphics processors and crt controllers have the ability of generating horizontal sync (hsync), vertical sync (vsync) and composite sync . in a graphics system that does not automatically generate a composite sync signal, the inclusion of some additional logic circuitry will enable the generation of a composite sync signal. the sync current is internally connected directly to the iog output, thus encoding video synchronization information onto the green video channel. if it is not required to encode sync information onto the ADV7123, the sync input should be tied to logic low. reference input the ADV7123 contains an onboard voltage reference. the v ref pin is normally terminated to v aa through a 0.1 m f capacitor. alternatively, the part could, if required, be overdriven by an external 1.23 v reference (ad1580). a resistance r set connected between the r set pin and gnd determines the amplitude of the output video level according to equations 1, 2 for the ADV7123: iog * ( ma ) = 12,081 v ref (v)/ r set ( w ) (1) ior, iob (ma) = 8,627 v ref (v)/r set ( w ) (2) * applies to the ADV7123 only when sync is being used. if sync is not being encoded onto the green channel, equation 1 will be similar to equation 2. using a variable value of r set , as shown in figure 22, allows for accurate adjustment of the analog output video levels. use of a fixed 560 w r set resistor yields the analog output levels as quoted in the specification page. these values typically correspond to the rs-343a video waveform values as shown in figure 21. d/a converters the ADV7123 contains three matched 10-bit d/a converters. the dacs are designed using an advanced, high speed, seg- mented architecture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. as all this circuitry is on one monolithic device, matching between the three dacs is optimized. as well as matching, the use of identi- cal current sources in a monolithic design guarantees monoto- nicity and low glitch. the onboard operational amplifier stabilizes the full-scale output current against temperature and power supply variations. analog outputs the ADV7123 has three analog outputs, corresponding to the red, green and blue video signals. the red, green and blue analog outputs of the ADV7123 are high impedance current sources. each one of these three rgb current outputs is capable of directly driving a 37.5 w load, such as a doubly terminated 75 w coaxial cable. figure 22a shows the required configuration for each of the three rgb outputs con- nected into a doubly terminated 75 w load. this arrangement will develop rs-343a video output voltage levels across a 75 w monitor. a suggested method of driving rs-170 video levels into a 75 w monitor is shown in figure 22b. the output current levels of the dacs remain unchanged, but the source termination resistance, z s , on each of the three dacs is increased from 75 w to 150 w . ior, iog, iob z o = 75 v (cable) z s = 75 v (source termination) termination repeated three times for red, green and blue dacs z l = 75 v (monitor) dacs figure 22a. analog output termination for rs-343a ior, iog, iob z o = 75 v (cable) z s = 150 v (source termination) termination repeated three times for red, green and blue dacs z l = 75 v (monitor) dacs figure 22b. analog output termination for rs-170 more detailed information regarding load terminations for vari- ous output configurations, including rs-343a and rs-170, is available in an application note entitled video formats & required load terminations available from analog devices, publication no. e1228C15C1/89. figure 21 shows the video waveforms associated with the three rgb outputs driving the doubly terminated 75 w load of figure 22a. as well as the gray scale levels, black level to white level, the diagram also shows the contributions of sync and blank for the ADV7123. these control inputs add appropriately weighted currents to the analog outputs, producing the spe- cific output level requirements for video applications. table i details how the sync and blank inputs modify the output levels. gray scale operation the ADV7123 can be used for stand-alone, gray scale (mono- chrome) or composite video applications (i.e., only one channel used for video information). any one of the three channels, red, green or blue can be used to input the digital video data. the two unused video data channels should be tied to logical zero. the unused analog outputs should be terminated with the same load as that for the used channel. in other words, if the red channel is used and ior is terminated with a doubly terminated 75 w load (37.5 w ), iob and iog should be termi- nated with 37.5 w resistors. see figure 23.
ADV7123 C15C rev. a ground planes the ADV7123 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. this ground plane should connect to the regular pcb ground plane at a single point through a ferrite bead, as illustrated in figure 25. this bead should be located as close as possible (within three inches) to the ADV7123. the analog ground plane should encompass all ADV7123 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. the regular pcb ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7123. power planes the pc board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. the analog power plane should encompass the ADV7123 (v aa ) and all associated analog circuitry. this power plane should be con- nected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as illustrated in figure 25. this bead should be loc ated within three inc hes of the ADV7123. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all ADV7123 power pins, voltage reference circuitry and any output amplifiers. the pcb power and ground planes should not overlay portions of the analog power plane. keeping the pcb power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. supply decoupling noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see figure 25). optimum performance is achieved by the use of 0.1 m f ceramic capacitors. each of the two groups of v aa should be individually decoupled to ground. this should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. it is important to note that while the ADV7123 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise. a dc power supply filter (murata bnx002) will pro- vide emi suppression between the switching power supply and the main pcb. alternatively, consideration could be given to using a three terminal voltage regulator. digital signal interconnect the digital signal lines to the ADV7123 should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the ADV7123 should be avoided to minimize noise pickup. gnd ADV7123 r0 r9 g0 g9 b0 b9 video input doubly terminated 75 v load ior iog iob 37.5 v 37.5 v figure 23. input and output connections for stand-alone gray scale or composite video video output buffers the ADV7123 is specified to drive transmission line loads, as are most monitors rated. the analog output configurations to drive such loads are described in the analog interface section and illustrated in figure 23. however, in some applications it may be required to drive long transmission line cable lengths. cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. the inclusion of output buffers will compensate for some cable distortion. buffers with large full power bandwidths and gains between two and four will be required. these buffers will also need to be able to sup- ply sufficient current over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad84x series of m onol ithic op amps. in very high frequency applications (80 mhz), the ad9617 is recommended. more information on line driver buffering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit will result in any desired video level. ad848 0.1 m f ior, iog, iob z 1 z 2 z o = 75 v (cable) z s = 75 v (source termination) z l = 75 v (monitor) dacs 75 v Cv s +v s 0.1 m f gain (g) = 1 + z 1 z 2 figure 24. ad848 as an output buffer pc board layout considerations the ADV7123 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the ADV7123, it is imperative that great care be given to the pc board layout. figure 25 shows a recommended connection diagram for the ADV7123. the layout should be optimized for lowest noise on the ADV7123 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should by minimized to minimize inductive ringing.
C16C any active pull-up termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not the analog power plane. analog signal interconnect the ADV7123 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. gnd r set ior iog iob ADV7123 75 v comp complementary outputs r9Cr0 g9Cg0 b9Cb0 clock sync psave video data inputs analog ground plane l1 (ferrite bead) v aa v ref r set 560 v ior iog iob 75 v 75 v blank 75 v 75 v 75 v 0.1 m f 0.1 m f 10 m f 0.01 m f 33 m f 0.1 m f +5v (v aa ) power supply decoupling (0.1 m f and 0.01 m f capacitor for each v aa group) coaxial cable 75 v 13, 29, 30 25, 26 39-48 1-10 14-23 monitor (crt) bnc connectors +5v (v aa ) v cc v aa figure 25. typical connection diagram for optimum performance, the analog outputs should each have a source terminat ion resistance to ground of 75 w (doubly terminated 75 w configuration). this termination resistance should be as close as possible to the ADV7123 to minimize reflections. additional information on pcb design is available in an applica- tion note entitled design and layout of a video graphics system for reduced emi. this application note is available from analog devices, publication no. e1309C15C10/89. outline dimensions dimensions shown in inches and (mm). 48-lead lqfp (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 C 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09) c3259aC0C6/98 printed in u.s.a. ADV7123 rev. a

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